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LTC2941 Battery Gas Gauge with I2C Interface FEATURES
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DESCRIPTION
The LTC(R)2941 measures battery charge state in batterysupplied handheld PC and portable product applications. Its operating range is perfectly suited for single cell Li-Ion batteries. A precision coulomb counter integrates current through a sense resistor between the battery's positive terminal and the load or charger. The measured charge is stored in internal registers. An SMBus/I2C interface accesses and configures the device. The LTC2941 features programmable high and low thresholds for accumulated charge. If a threshold is exceeded, the device communicates an alert using either the SMBus alert protocol or by setting a flag in the internal status register. The LTC2941 requires only a single low value external sense resistor to set the current range.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Indicates Accumulated Battery Charge and Discharge High Accuracy Analog Integration High Side Sense 1% Charge Accuracy 50mV Sense Voltage Range SMBus/I2C Interface Configurable Alert Output/Charge Complete Input 2.7V to 5.5V Operating Range Quiescent Current Less than 100A Small 6-Pin 2mm x 3mm DFN package
APPLICATIONS
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Low Power Handheld Products Cellular Phones MP3 Player Cameras GPS
TYPICAL APPLICATION
Total Charge Error vs Differential Sense Voltage
CHARGER SENSE+ LTC2941 AL/CC SDA SENSE- SCL GND LOAD 0.1F RSENSE 100m 2.0 1.5 CHARGE ERROR (%) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0.1 1 VSENSE (mV)
2941 TA01b
VSENSE+ = 3.6V
I2C/SMBus TO HOST
+
1-CELL Li-Ion
2941 TA01a
10
100
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LTC2941 ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
PIN CONFIGURATION
TOP VIEW SENSE+ 1 GND 2 SCL 3 7 GND 6 SENSE- 5 AL/CC 4 SDA
Supply Voltage (SENSE+) ............................. -0.3V to 6V SCL, SDA, AL/CC ......................................... -0.3V to 6V SENSE- .................................. -0.3V to (VSENSE+ + 0.3V) Operating Ambient Temperature Range LTC2941C ................................................ 0C to 70C LTC2941I.............................................. -40C to 85C Storage Temperature Range..................... -65C to 150
DCB PACKAGE 6-LEAD (2mm x 3mm) PLASTIC DFN TJMAX = 150C, JA = 120C/W EXPOSED PAD (PIN 7) IS GND, MUST BE SOLDERED TO PCB OR LEFT FLOATING
ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI) LTC2941CDCB#TRMPBF TAPE AND REEL LTC2941CDCB#TRPBF PART MARKING* LFKQ PACKAGE DESCRIPTION 6-Lead (2mm x 3mm) Plastic DFN TEMPERATURE RANGE 0C to 70C -40C to 85C
LTC2941IDCB#TRMPBF LTC2941IDCB#TRPBF LFKQ 6-Lead (2mm x 3mm) Plastic DFN TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
SYMBOL VSENSE+ ISUPPLY PARAMETER Supply Voltage Supply Current (Note 3) Power Requirements
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2)
CONDITIONS MIN 2.7 Device On Shutdown Shutdown, VSENSE+ 4.2V
l l l l
TYP
MAX 5.5
UNITS V A A A V mV k mAh
70
100 2.5 1
VUVLO VSENSE
Undervoltage Lockout Threshold Sense Voltage Differential Input Range Differential Input Resistance, Across SENSE+ and SENSE- (Note 7)
VSENSE+ Falling VSENSE+ - VSENSE-
2.5
2.6
2.7 50
Coulomb Counter 400 Prescaler M = 128 (Default), RSENSE = 50m 10mV |VSENSE | 50mV DC 10mV |VSENSE | 50mV, DC VSENSE+ 4.2V 1mV |VSENSE | 50mV DC (Note 7) Vbat Alert Vbat Alert Threshold VSENSE+ Falling, B[7:6] = 01 VSENSE+ Falling, B[7:6] = 10 VSENSE+ Falling, B[7:6] = 11
l l l l l
qLSB TCE
Charge LSB (Note 4) Total Charge Error (Note 5)
0.085 1 1.5 3.5 2.75 2.85 2.95 2.8 2.9 3 2.85 2.95 3.05
% % % V V V
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LTC2941 ELECTRICAL CHARACTERISTICS
SYMBOL VITH VOL IIN CIN tPCC PARAMETER Logic Input Threshold, AL/CC, SCL, SDA Low Level Output Voltage, AL/CC, SDA I = 3mA Input Leakage, AL/CC, SCL, SDA Input Capacitance, AL/CC, SCL, SDA Minimum Charge Complete (CC) Pulse Width Maximum SCL Clock Frequency Bus Free Time Between Stop/Start Minimum Repeated Start Setup Time Minimum Hold Time (Repeated) Start Condition
l l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2)
CONDITIONS
l l l l
MIN 0.3 * VSENSE+
TYP
MAX 0.7 * VSENSE+ 0.4 1 10 1
UNITS V V A pF s
Digital Inputs and Digital Outputs
VIN = VSENSE+/2 (Note 7)
I2C Timing Characteristics fSCL(MAX) tBUF(MIN) tSU,STA(MIN) tHD,STA(MIN) 400 900 1.3 600 600 600 100 0 kHz s ns ns ns ns s
tSU,STO(MIN) Minimum Setup Time for Stop Condition tSU,DAT(MIN) Minimum Data Setup Time Input tHD,DATI(MIN) Minimum Data Hold Time Input Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive, all voltages are referenced to GND unless otherwise specified Note 3: ISUPPLY = ISENSE+ + ISENSE- Note 4: The equivalent charge of an LSB in the accumulated charge registers (C,D) depends on the value of RSENSE and the setting of the
internal pre-scaling factor M. It is calculated by: 50m M qLSB = 0.085mAh * * RSENSE 128 See Choosing RSENSE and Coulomb Counter Prescaler M section for more information. 1mAh = 3.6A * s = 3.6C (Coulomb), 0.085mAh = 306mC. Note 5: Deviation of qLSB from its nominal value. Note 6: CB = capacitance of one bus line in pF (10pF CB 400pF). Note 7: Guaranteed by design, not subject to test.
TIMING DIAGRAM
tof SDA tSU, DAT tHD, DATO, tHD, DATI tSU, STA tHD, STA tBUF tSU, STO
2941 F01
SCL tHD, STA
START CONDITION
REPEATED START CONDITION
STOP CONDITION
START CONDITION
Figure 1. Definition of Timing on I2C Bus
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LTC2941 TYPICAL PERFORMANCE CHARACTERISTICS
Total Charge Error vs Differential Sense Voltage
3 2 CHARGE ERROR (%) 1 0 -1 -2 -3 0.1 VSENSE+ = 2.7V VSENSE+ = 4.2V 1 VSENSE (mV)
2941 G01
Total Charge Error vs Supply Voltage
1.00 0.75 CHARGE ERROR (%) CHARGE ERROR (%) 0.50 0.25 0 1.00 0.75 0.50 0.25 0 -0.25 -0.50 VSENSE = -50mV VSENSE = -10mV 2.5 3.0 3.5 4.0 4.5 5.0 VSENSE+ (V) 5.5 6.0 -0.75
Total Charge Error vs Temperature
-0.25 -0.50 -0.75 -1.00
10
100
-1.00 -50
VSENSE = -50mV VSENSE = -10mV -25 25 0 50 TEMPERATURE (C) 75 100
2941 G03
2941 G02
Supply Current vs Supply Voltage
100 90 80 70 60 50 40 2.5 0 TA = 25C TA = -40C TA = 85C 1.5 ISHUTDOWN (A) ISUPPLY (A) 2.0
Shutdown Supply Current vs Supply Voltage
1.0
0.5 TA = 25C TA = -40C TA = 85C 3.0 3.5 4.0 4.5 5.0 VSENSE+ (V) 5.5 6.0 2.5 3.0 3.5 4.0 4.5 5.0 VSENSE+ (V) 5.5 6.0
2941 G04
2941 G05
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LTC2941 PIN FUNCTIONS
SENSE+ (Pin 1): Positive Current Sense Input and Power Supply. Connect to the load/charger side of the sense resistor. VSENSE+ operating range is 2.7V to 5.5V. GND (Pin 2, Exposed Pad Pin 7): Device Ground. Connect directly to the negative battery terminal. Exposed pad may be left open or connected to device ground. SCL (Pin 3): Serial Bus Clock Input. SDA (Pin 4): Serial Bus Data Input and Output. AL/CC (Pin 5): Alert Output or Charge Complete Input. Configured either as an SMBus alert output or charge complete input by control register bits B[2:1]. At power-up, the pin defaults to alert mode conforming to the SMBus alert response protocol. It behaves as an open-drain logic output that pulls to GND when a value in the threshold registers is exceeded. When configured as a charge complete input, connect to the charge complete output from the battery charger circuit. A high level at CC sets the value of the accumulated charge (registers C, D) to FFFFh. SENSE- (Pin 6): Negative Current Sense Input. Connect SENSE- to the positive battery terminal side of the sense resistor. The voltage between SENSE- and SENSE+ must remain within 50mV in normal operation.
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LTC2941 BLOCK DIAGRAM
VSUPPLY 1 SENSE+ BIDIRECTIONAL INTEGRATOR REF 2 GND INTERNAL REFERENCE GENERATOR INTERNAL OSCILLATOR CLK I2C/ SMBus STATUS/ CONTROL REGISTER SCL SDA 3 PRESCALER M ACCUMULATED CHARGE REGISTER CC AL AL/CC
6
SENSE-
5
4
2941 F02
Figure 2. Block Diagram of the LTC2941
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LTC2941 OPERATION
Overview The LTC2941 is a battery gas gauge device designed for use with single Li-Ion cells and other battery types with a terminal voltage between 2.7V and 5.5V. A precision coulomb counter integrates current through a sense resistor between the battery's positive terminal and the load or charger. Coulomb Counter Charge is the time integral of current. The LTC2941 measures battery current by monitoring the voltage developed across a sense resistor and then integrates this information to infer charge. The differential voltage between SENSE+ and SENSE- is applied to an auto-zeroed differential analog integrator to convert the measured current to charge. When the integrator output ramps to REFHI or REFLO levels, switches S1, S2, S3 and S4 toggle to reverse the ramp direction. By observing the condition of the switches and the ramp direction, polarity is determined. A programmable prescaler is incremented or decremented every time the integrator changes ramp direction. The prescaler effectively increases integration time by a factor M programmable from 1 to 128. At each under or overflow of the prescaler, the accumulated charge is incremented or decremented one count. The value of accumulated charge is read via the I2C interface. Power-Up Sequence When VSENSE+ rises above a threshold of approximately 2.5V, the LTC2941 generates an internal power-on reset (POR) signal and sets all registers to their default state. In the default state, the coulomb counter is active. The accumulated charge is set to mid-scale (7FFFh), the low threshold registers are set to 0000h and all the high threshold registers are set to FFFFh. The alert mode is enabled and the coulomb counter pre-scaling factor M is set to 128.
STATUS CHARGER LOAD VSUPPLY 1 RSENSE IBAT 6 SENSE- S4 GND REFLO SENSE+ S1 REFHI
+
CONTROL LOGIC
CONTROL AL/CC REGISTERS PRESCALER M I2C/ SMBus ACR POLARITY DETECTION SCL SDA
-
5 3 4
S2
BATTERY
+
2
Figure 3. Coulomb Counter Section of the LTC2941
+
S3
-
+ -
THRESHOLDS
2941 F03
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LTC2941 APPLICATIONS INFORMATION
I2C/SMBus Interface The LTC2941 communicates with a bus master using a 2-wire interface compatible with I2C and SMBus. The 7-bit hard-coded I2C address of LTC2941 is 1100100. The LTC2941 is a slave-only device. Therefore the serial clock line (SCL) is input only while the data line (SDA) is bidirectional. For more details refer to the I2C Protocol section. Internal Registers The LTC2941 integrates current through a sense resistor and stores a 16-bit result, accumulated charge, as two bytes in registers C and D. Two byte high and low limits programmed in registers E, F G and H are continuously , compared against the accumulated charge. If either limit is exceeded, a corresponding flag is set in the status register bits A[2] or A[3]. If the alert mode is enabled, the AL/CC pin pulls low. The internal eight registers are organized as shown in Table 1:
Table 1. Register Map
ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h NAME REGISTER DESCRIPTION A B C D E F G H Status Control Accumulated Charge MSB Accumulated Charge LSB Charge Threshold High MSB Charge Threshold High LSB Charge Threshold Low MSB Charge Threshold Low LSB R/W R R/W R/W R/W R/W R/W R/W R/W DEFAULT See Below 3Ch 7Fh FFh FFh FFh 00h 00h
Status Register (A) Table 2 shows the details of the status register (address 00h):
Table 2. Status Register A (Read Only)
BIT NAME A[7] Chip Identification A[6] Reserved A[5] Accumulated Charge Overflow/Underflow A[4] Reserved A[3] Charge Alert High OPERATION 1: LTC2941 0: LTC2942 Not Used. Indicates that the value of the accumulated charge hit either top or bottom. Not used. Indicates that the accumulated charge value exceeded the charge threshold high limit. Indicates that the accumulated charge value dropped below the charge threshold low limit. Indicates that the battery voltage (at SENSE-) dropped below selected VBAT threshold. Indicates recovery from undervoltage. If equal to 1, a UVLO has occurred and the content of registers is uncertain. DEFAULT 1 0 0
0 0
A[2] Charge Alert Low
0
A[1] VBAT Alert
0
A[0] Undervoltage Lockout Alert
X
The AL/CC pin can be configured to pull low whenever any status register bit is set (except for bit A[7] and A[0]), using control register bits B[2] and B[1]. All status register bits except A[7] are cleared after being read by the host if the conditions which set these bits have been removed. As soon as one of the measured quantities exceeds the programmed limits, the corresponding bit A[3], A[2] or A[1] in the status register is set.
R = Read, W = Write
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LTC2941 APPLICATIONS INFORMATION
Bit A[5] is set if the LTC2941's accumulated charge overflows or underflows the combined total in registers C and D. Note that the counting process does not roll over, but simply stops at FFFFh or 0000h until the direction is reversed. The LTC2941 includes a battery undervoltage monitor, which sets bit A1 if the limit is exceeded. Limits are selected in the control register. The undervoltage lockout (UVLO) bit A[0] is set if, during operation, the voltage on SENSE+ drops below 2.7V without reaching the POR level. The analog parts of the coulomb counter are switched off while the digital register values are retained. After recovery of the supply voltage the coulomb counter resumes integrating with the stored value in the accumulated charge registers (C, D) but it has missed any charge flowing while VSENSE+ < 2.7V. The hard coded bit A[7] of the status register enables the host to distinguish the LTC2941 from the pin compatible LTC2942, allowing the same software to be used with both devices. Control Register (B) The operation of the LTC2941 can be controlled by programming the control register at address 01h. Table 3 shows the organization of the 8-bit control register B[7:0]
Table 3. Control Register B
BIT NAME OPERATION [11] Threshold Value = 3.0V. [10] Threshold Value = 2.9V. [01] Threshold Value = 2.8V. [00] VBAT Alert Off. DEFAULT [00] B[7:6] VBAT Alert
Power Down B[0] Programming the last bit B[0] of the control register to 1 sets the analog parts of the LTC2941 in power down and the current consumption drops typically below 1A. All analog circuits are disabled while the values in the registers are retained. Note that any charge flowing while B[0] is 1 is not measured and the charge information below 1 LSB of the accumulated charge register is lost. Alert/Charge Complete Configuration B[2:1] The AL/CC pin is a dual function pin configured by the control register. By setting bits B[2:1] to [10] (default) the AL/CC pin is configured as an alert pin following the SMBus protocol. In this alert mode the AL/CC pin is a digital output and is pulled low if one of the measured quantities exceeds its high or low threshold or if the an overflow/underflow occurs in the accumulated charge registers C and D. An alert response procedure started by the master resets the alert at the AL/CC pin. For further information see the Alert Response Protocol section. Setting the control bits B[2:1] to [01] configures the AL/CC pin as a digital input. In this mode, a high input on the AL/CC pin communicates to the LTC2941 that the battery is full and the accumulated charge is set to its maximum value FFFFh. The AL/CC pin would typically be connected to the "charge complete" output from the battery charger circuitry. If neither the alert nor the charge complete functionality is desired, bits B[2:1] should be set to [00]. The AL/CC pin is then disabled and should be tied to GND. Avoid setting B[2:1] to [11] as it enables the alert and the charge complete modes simultaneously. Choosing RSENSE and Coulomb Counter Prescaler "M" B[5:3] To achieve the specified precision of the coulomb counter the differential voltage between SENSE+ and SENSE- must stay within 50mV. For differential input signals up to 300mV the LTC2941 will remain functional but the precision of the coulomb counter is not guaranteed.
B[5:3] Prescaler M Sets coulomb counter prescaling factor M between 1 and 128. Default is 128. M = 2(4 * B[5] + 2 * B[4] + B[3]). B[2:1] AL/CC Configure Configures the AL/CC pin. [10] Alert Mode. Alert functionality enabled. Pin becomes logic output. [01] Charge Complete Mode. Pin becomes logic input and accepts "charge complete" signal (e.g., from a charger) to set accumulated charge Register to FFFFh. [00] AL/CC pin disabled. [11] Not allowed. B[0] Shutdown Shut down analog section to reduce ISUPPLY.
[111]
[10]
[0]
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LTC2941 APPLICATIONS INFORMATION
The value of the external sense resistor is determined by the maximum input range of VSENSE and the maximum current of the application: RSENSE 50mV IMAX exhausted or overflow during charge. Choose in this case a maximum RSENSE of: RSENSE 0.085mAh * 216 * 50m QBAT
The choice of the external sense resistor value influences the gain of the coulomb counter. A larger sense resistor gives a larger differential voltage between SENSE+ and SENSE- for the same current which results in more precise coulomb counting. Thus the amount of charge represented by the least significant bit (qLSB) of the accumulated charge (registers C, D) is given by: qLSB = 0.085mAh * or qLSB = 0.085mAh * 50m RSENSE 50m M * RSENSE 128
In an example application where the maximum current is IMAX = 100mA, calculating RSENSE = 50mV/IMAX would lead to a sense resistor of 500m. This gives a qLSB of 8.5Ah and the accumulated charge register can represent a maximum battery capacity of QBAT = 8.5Ah * 65535 = 557mAh. If the battery is larger, RSENSE must be lowered. For example, RSENSE must be reduced to 150m if a battery with a capacity of 1800mAh is used. For case B: In applications using a small battery but having a high maximum current, qLSB can get quite large with respect to the battery capacity. For example, if the battery capacity is 100mAh and the maximum current is 1A, the standard equation leads to choose a sense resistor value of 50m, resulting in: qLSB = 0.085mAh = 306mC The battery capacity then corresponds to only 1176 qLSBs and less than 2% of the accumulated charge register is utilized. To preserve digital resolution in this case, the LTC2941 includes a programmable prescaler. Lowering the prescaler factor M allows reducing qLSB to better match the accumulated charge registers C and D to the capacity of the battery. The prescaling factor M can be chosen between 1 and its default value 128. The charge LSB then becomes: qLSB = 0.085mAh * 50m M * RSENSE 128
when the prescaler is set to its default value of M=128. Note that 1mAh = 3.6A*s = 3.6C (coulombs). Choosing RSENSE = 50mV/IMAX is not sufficient in applications where: A. the battery capacity (QBAT) is very large compared to the maximum current (IMAX): QBAT > IMAX * 5.5 hours B. the battery capacity (QBAT) is very small compared to the maximum current (IMAX): QBAT < IMAX * 0.1 hours For case A: In low current applications using a large battery, choosing RSENSE according to RSENSE = 50mV/IMAX can lead to a qLSB smaller than QBAT/216 and the 16-bit accumulated charge may underflow before the battery is
To use as much of the range of the accumulated charge registers C and D as possible the prescaler factor M should
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LTC2941 APPLICATIONS INFORMATION
be chosen for a given battery capacity QBAT and a sense resistor RSENSE as: M128 * 2
16
RSENSE * 0.085mAh 50m QBAT *
M can be set to 1, 2, 4, 8, ...128 by programming B[5:3] of the control register as M = 2(4 * B[5] + 2 * B[4] + B[3]). The default value after power up is M = 128 = 27 (B[5:3] = 111). In the above example of a 100mAh battery and a RSENSE of 50m, the prescaler should be programmed to M = 4. The qLSB then becomes 2.656Ah and the battery capacity corresponds to roughly 37650 qLSBs. Note that the internal digital resolution of the coulomb counter is higher than indicated by qLSB. The digitized charge qINTERNAL is M * 8 smaller than qLSB. qINTERNAL is typically 299As for a 50m sense resistor. VBAT Alert B[7:6] The VBAT alert function allows the LTC2941 to monitor the voltage at SENSE-. If enabled, a drop of the voltage at the SENSE- pin below a preset threshold is detected and bit A[1] in the status register is set. If the alert mode is enabled by setting B[2] to one, an alert is generated at the AL/CC pin. The threshold for the VBAT alert function is selectable according to Table 3. Accumulated Charge Registers (C,D) The coulomb counter of the LTC2941 integrates current through the sense resistor. The 16-bit result of this charge integration is stored in the accumulated charge registers C and D. As the LTC2941 does not know the actual battery status after initial power-up, the accumulated charge is set to mid-scale (7FFFh). If the host knows the status of the battery , the accumulated charge registers C[7:0] and D[7:0] can be either programmed to the correct value via I2C or it can be set after charging to FFFFh (full) by pulling the AL/CC pin high (if charge complete mode is enabled
via bits B[2:1]). Before writing the accumulated charge registers, the analog section should be shut down by setting B[0] to 1. In order to avoid a change in the accumulated charge registers between reading MSBs C[7:0] and LSBs D[7:0], it is recommended to read them sequentially as shown in Figure 8. Threshold Registers (E, F), (G, H) For battery charge, the LTC2941 features a high and a low threshold register. At power-up the high threshold is set to FFFFh while the low threshold is set to 0000h. Both thresholds can be programmed to a desired value via I2C. As soon as the accumulated charge exceeds the high threshold or falls below the low threshold, the LTC2941 sets the corresponding flag in the status register and pulls the AL/CC pin low if alert mode is enabled. I2C Protocol The LTC2941 uses an I2C/SMBus compatible 2-wire opendrain interface supporting multiple devices and masters on a single bus. The connected devices can only pull the bus wires low and they never drive the bus high. The bus wires should be externally connected to a positive supply voltage via a current source or pull-up resistor. When the bus is idle, both SDA and SCL are high. Data on the I2C-bus can be transferred at rates of up to 100kbit/s in standard mode and up to 400kbit/s in fast mode. Each device on the I2C/SMbus is recognized by a unique address stored in that device and can operate as either a transmitter or receiver, depending on the function of the device. In addition to transmitters and receivers, devices can also be classified as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At the same time any device addressed is considered a slave. The LTC2941 always acts as a slave. Figure 4 shows an overview of the data transmission on the I2C bus.
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LTC2941 APPLICATIONS INFORMATION
SDA a6 - a0 b7 - b0 b7 - b0
SCL S
1-7
8
9
1-7
8
9
1-7
8
9 P
ADDRESS START CONDITION
R/W
ACK
DATA
ACK
DATA
ACK STOP CONDITION
2941 F04
Figure 4. Data Transfer Over I2C or SMBus
Start and Stop Conditions When the bus is idle, both SCL and SDA must be high. A bus master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. When the bus is in use, it stays busy if a repeated START (Sr) is generated instead of a STOP condition. The repeated START (Sr) conditions are functionally identical to the START (S). Data Transmission After a START condition, the I2C bus is considered busy and data transfer begins between a master and a slave. As data is transferred over I2C in groups of nine bits (eight data bits followed by an acknowledge bit), each group takes nine SCL cycles. The transmitter releases the SDA line during the acknowledge clock pulse and the receiver issues an acknowledge (ACK) by pulling SDA low or leaves SDA high to indicate a not-acknowledge (NAK) condition. Change of data state can only happen while SCL is low. Write Protocol The master begins communication with a START condition followed by the seven bit slave address 1100100 and the R/W bit set to zero, as shown in Figure 5. The LTC2941 acknowledges this by pulling SDA low and then
the master sends a command byte which indicates which internal register the master is to write. The LTC2941 acknowledges and then latches the command byte into its internal register address pointer. The master delivers the data byte, the LTC2941 acknowledges once more and latches the data into the desired register. The transmission is ended when the master sends a STOP condition. If the master continues by sending a second data byte instead of a stop, the LTC2941 acknowledges again, increments its address pointer and latches the second data byte in the following register, as shown in Figure 6. Read Protocol The master begins a read operation with a START condition followed by the seven bit slave address 1100100 and the R/W bit set to zero, as shown in Figure 7. The LTC2941 acknowledges and then the master sends a command byte which indicates which internal register the master is to read. The LTC2941 acknowledges and then latches the command byte into its internal register address pointer. The master then sends a repeated START condition followed by the same seven bit address with the R/W bit now set to one. The LTC2941 acknowledges and sends the contents of the requested register. The transmission is ended when the master sends a STOP condition. If the master acknowledges the transmitted data byte, the LTC2941 increments its address pointer and sends the contents of the following register as shown in Figure 8.
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LTC2941 APPLICATIONS INFORMATION
Alert Response Protocol In a system where several slaves share a common interrupt line, the master can use the alert response address (ARA) to determine which device initiated the interrupt (Figure 9). The master initiates the ARA procedure with a START condition and the special 7-bit ARA bus address (0001100) followed by the read bit (R) = 1. If the LTC2941 is asserting the AL/CC pin in alert mode, it acknowledges and responds by sending its 7-bit bus address (1100100) and a 1. While
S
ADDRESS 1100100
W 0
A 0
REGISTER 01h
A 0
DATA FCh
A 0
P
2941 F05
FROM MASTER TO SLAVE FROM SLAVE TO MASTER
A: ACKNOWLEDGE (LOW) A: NOT-ACKNOWLEDGE (HIGH) R: READ BIT (HIGH) W: WRITE BIT (LOW) S: START CONDITION P: STOP CONDITION
Figure 5. Writing FCh to LTC2941 Control Register (B)
S
ADDRESS 1100100
W 0
A 0
REGISTER 02h
A 0
DATA F0h
A 0
DATA 01h
A 0
P
2941 F06
Figure 6. Writing F001h to the LTC2941 Accumulated Charge Registers (C, D)
S
ADDRESS 1100100
W 0
A 0
REGISTER 00h
A 0
S
ADDRESS 1100100
R 1
A 0
DATA 81h
A 1
P
2941 F07
Figure 7. Reading the LTC2941 Status Register (A)
S
ADDRESS 1100100
W 0
A 0
REGISTER 02h
A 0
S
ADDRESS 1100100
R 1
A 0
DATA 80h
A 0
DATA 01h
A 1
P
2941 F08
Figure 8. Reading the LTC2941 Accumulated Charge Registers (C, D)
S
ALERT RESPONSE ADDRESS 0001100
R 1
A 0
DEVICE ADDRESS 11001001
A 1
P
2941 F09
Figure 9. LTC2941 Serial Bus SDA Alert Response Protocol
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LTC2941 APPLICATIONS INFORMATION
it is sending its address, it monitors the SDA pin to see if another device is sending an address at the same time using standard I2C bus arbitration. If the LTC2941 is sending a 1 and reads a 0 on the SDA pin on the rising edge of SCL, it assumes another device with a lower address is sending and the LTC2941 immediately aborts its transfer and waits for the next ARA cycle to try again. If transfer is successfully completed, the LTC2941 will stop pulling down the AL/CC pin and will not respond to further ARA requests until a new alert event occurs. PC Board Layout Recommendations Keep all traces as short as possible to minimize noise and inaccuracy. Use a 4-wire Kelvin sense connection for the sense resistor, locating the LTC2941 close to the resistor with short sense traces to SENSE+ and SENSE-. Use wider traces from the resistor to the battery, load and/or charger (see Figure 10). Put the bypass capacitor close to SENSE+ and GND.
TO CHARGER/LOAD 1 C 2 3
RSENSE
TO BATTERY
6 LTC2941 5 4
2941 F10
Figure 10. Kelvin Connection on Sense Resistor
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14
LTC2941 PACKAGE DESCRIPTION
DCB Package 6-Lead Plastic DFN (2mm x 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)
0.70 0.05
3.55 0.05
1.65 0.05 (2 SIDES) PACKAGE OUTLINE
2.15 0.05
0.25 0.50 BSC 1.35 0.05 (2 SIDES)
0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 2.00 0.10 (2 SIDES) R = 0.115 TYP R = 0.05 TYP 0.40 4 6 0.10
3.00 0.10 (2 SIDES) PIN 1 BAR TOP MARK (SEE NOTE 6)
1.65 0.10 (2 SIDES) PIN 1 NOTCH R0.20 OR 0.25 45 CHAMFER 3 1 0.25 0.50 BSC 1.35 0.10 (2 SIDES)
(DCB6) DFN 0405
0.05
0.200 REF
0.75 0.05
0.00 - 0.05
BOTTOM VIEW--EXPOSED PAD
NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC2941 TYPICAL APPLICATION
Single Cell Lithium-Ion Coulomb Counter with Battery Charger for Charge and Discharge Currents of up to 500mA
500mA 3.3V 2k 1 VDD P 2k 2k 1 SENSE+ LTC2941 5 AL/CC 4 6 SDA SENSE- 3 SCL GND 2
2941 TA02
VIN 5V 1F
4
VCC
BAT
3
LOAD 0.1F
LTC4057-4.2 (CHARGER) 5 PROG SHDN GND 2
RSENSE 100m
2k
+
1-CELL Li-Ion
RELATED PARTS
PART NUMBER LTC2941-1 LTC2942 LTC2942-1 LTC4150 Battery Chargers LTC1734 LTC4002 LTC4052 LTC4053 LTC4057 LTC4058 LTC4059 LTC4061 LTC4063 LTC4080 LTC4088 Lithium-Ion Battery Charger in ThinSOTTM Switch Mode Lithium-Ion Battery Charger Monolithic Lithium-Ion Battery Pulse Charger USB Compatible Monolithic Li-Ion Battery Charger Lithium-Ion Linear Battery Charger Standalone 950mA Lithium-Ion Charger in DFN 900mA Linear Lithium-Ion Battery Charger Standalone Linear Li-Ion Battery Charger with Thermistor Input Li-Ion Charger with Linear Regulator 500mA Standalone Li-Ion Charger with Integrated 300mA Synchronous Buck High Efficiency Battery Charger/USB Power Manager Maximizes Available Power from USB Port, Bat-TrackTM, Instant-On Operation, 1.5A Max Charge Current, 180m Ideal Diode with <50m Option, 3.3V/25mA Always-On LDO, 4mm x 3mm DFN-14 Package Simple ThinSOT Charger, No Blocking Diode, No Sense Resistor Needed Standalone, 4.7V VIN 24V, 500kHz Frequency No Blocking Diode or External Power FET Required, 1.5A Charge Current Standalone Charger with Programmable Timer, Up to 1.25A Charge Current Up to 800mA Charge Current, Thermal Regulation, ThinSOT Package C/10 Charge Termination, Battery Kelvin Sensing, 7% Charge Accuracy 2mm x 2mm DFN Package, Thermal Regulation, Charge Current Monitor Output 4.2V, 0.35% Float Voltage, Up to 1A Charge Current, 3mm x 3mm DFN Package Up to 1A Charge Current, 100mA, 125mV LDO, 3mm x 3mm DFN Package DESCRIPTION Battery Gas Gauge with I2C Interface and integrated 50m Sense Resistor Battery Gas Gauge with I2C Interface, Voltage and Temperature Measurement Battery Gas Gauge with I2C Interface and Voltage and Temperature ADC; Integrated Sense Resistor Coulomb Counter/Battery Gas Gauge COMMENTS Pin Compatible with LTC2942-1 14-Bit -ADC, Pin Compatible with LTC2941 14-Bit -ADC, Pin Compatible with LTC2941-1 2.7V to 8.5V Operation, 10-Pin MSOP Package Battery Gas Gauges
ThinSOT and Bat-Track are trademarks of Linear Technology Corporation.
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16 Linear Technology Corporation
(408) 432-1900
LT 0210 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
FAX: (408) 434-0507 www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2010

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